VHDL'DE D - FLIP FLOP DEVRESİ

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity dflipflop is
port ( D : in std_logic;
CLK : in std_logic;
Q : inout std_logic;
QN : inout std_logic
);
end dflipflop;

architecture Behavioral of dflipflop is

begin
process(D,CLK)
begin
if CLK' event and CLK='1' then
Q <= D;
QN <= NOT D;
end if;
end process;
end Behavioral;

-------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Circuit is
port ( X : in std_logic;
CLK : in std_logic;
Z : out std_logic
);
end Circuit;

architecture Structural of Circuit is

component dff is
port ( D : in std_logic;
CLK : in std_logic;
Q : inout std_logic;
QN : inout std_logic
);
end component;

signal S2: std_logic_vector (1 downto 0);
signal Q1,Q1N,Q2,Q2N : std_logic;

begin
S2(0) <=  Q1N OR Q2;
S2(1) <= Q2N AND X;
DFF1: dff port map (S2(0),CLK,Q1,Q1N);
DFF2: dff port map (S2(1),CLK,Q2,Q2N);
Z <= Q1 OR Q2N;

end Structural;

VHDL'DE 4 BİTLİK TAM TOPLAYICI / ÇIKARICI DEVRESİ

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity fullAdder is
   port( X : in std_logic;
Y : in std_logic;
Cin : in std_logic;
sum : out std_logic;
Cout : out std_logic);
end fullAdder;

architecture data_flow of fullAdder is

begin

   sum <= (X XOR Y) XOR Cin;
   Cout <= ((X XOR Y) AND Cin) OR (X AND Y);

end data_flow;

--------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity fourBitsAdderSubtractor is
   port( S : in std_logic;
A  : in std_logic_vector(3 downto 0);
B  : in std_logic_vector(3 downto 0);
SUM  : out std_logic_vector(3 downto 0);
Cout : out std_logic);
end fourBitsAdderSubtractor;

architecture Structural of fourBitsAdderSubtractor is
component fullAdder is        
   port( X : in std_logic;
Y : in std_logic;
Cin : in std_logic;
sum : out std_logic;
Cout : out std_logic);
end component;

signal C: std_logic_vector(3 downto 0);
signal TMP: std_logic_vector(3 downto 0);

begin
TMP(0) <= B(0) XOR S;
TMP(1) <= B(1) XOR S;
TMP(2) <= B(2) XOR S;
TMP(3) <= B(3) XOR S;

FA0: fullAdder port map(A(0), TMP(0), S, SUM(0), C(0));
FA1: fullAdder port map(A(1), TMP(1), C(0), SUM(1), C(1));
FA2: fullAdder port map(A(2), TMP(2), C(1), SUM(2), C(2));
FA3: fullAdder port map(A(3), TMP(3), C(2), SUM(3), C(3));

Cout <= C(3);

end Structural;

VHDL'DE KOD ÇÖZÜCÜ DEVRESİ

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Decoder_2_to_4 is

port ( w: in std_logic_vector(1 downto 0);

E: in std_logic;

y: out std_logic_vector( 3 downto 0)

);

end Decoder_2_to_4;

architecture Behavioral of Decoder_2_to_4 is

begin

process (w,E)

begin

if(E='1') then

case w is

when "00"=> y(0) <='1';

when "01"=> y(1) <='1';

when "10"=> y(2) <='1';

when "11"=> y(3) <='1';

when others => y <="1111";

end case;

else

y <="0000";

end if;

end process;

end Behavioral;

----------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity Circuit is

port ( W: in std_logic_vector (2 downto 0);

EN:  in std_logic;

Y: out std_logic_vector (7 downto 0)

);      

end Circuit;

architecture Structural of Circuit is

component Decoder_2_to_4 is

port ( w: in std_logic_vector(1 downto 0);

E: in std_logic;

y: out std_logic_vector( 3 downto 0)

);

end component;

signal temp : STD_LOGIC_VECTOR(2 downto 0);

begin

temp(0) <= NOT W(2);

temp(1) <= temp(0) AND EN;

temp(2) <= W(2) AND EN;

DEC1: Decoder_2_to_4 port map(W(1 downto 0),temp(1),Y(3 downto 0));

DEC2: Decoder_2_to_4 port map(W(1 downto 0),temp(2),Y(7 downto 4));

end Structural;

C'DE OBEB - OKEK HESABI

#include <stdio.h>

int greatestCommonDivisor(int x, int y){
if (x == 0){
return y;
}

while (y != 0){
if (x > y){
x = x - y;
}
else{
y = y - x;
}
}
return x;
}

int greatestCommonDivisor2(int x, int y){
int temp;
if (x == 0){
return y;
}

while (y != 0){
temp = y;
y = x % y;
x = temp;
}
return x;
}

int main(){
int x, y, gcd, lcm;
printf("Print any negative number to exit!!!\n\n");
while (1){
printf("Enter the numbers : ");
scanf("%d%d", &x, &y);
if (x < 0 || y < 0){
break;
}
else if (x == 0 && y == 0){
printf("If numbers are equal to zero, GCD is uncertain. LCM : 0\n\n");
}
else if (x == 0 || y == 0){
gcd = greatestCommonDivisor(x, y);
printf("If one of the numbers is equal to zero, LCM is undefined. GCD : %d\n\n", gcd);
}
else if (x == y){
printf("GCD = LCM = %d\n", x);
}
else{
gcd = greatestCommonDivisor(x, y);
//gcd = greatestCommonDivisor2(x, y);
lcm = (x * y) / gcd;
printf("Greatest Common Divisor : %d\n", gcd);
printf("Least Common Multiple : %d\n\n", lcm);
}
}
}

greatestCommonDivisor ve greatestCommonDivisor2 aynı işi yapan fakat farklı algoritmalar kullanan fonksiyonlardır.